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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. features ata compatibility ? 3.3v or 5.0v single power supply. ? 68 pin two piece connector with type-2 form factor (5mm thickness) ? support for cis implementation with 256 bytes of attribute memory interface modes ? pc card memory mode ? pc card i/o mode ? true ide mode high performance ? interface transfer speed in pio mode 4 or multi word dma mode 2 cycle timing, 16.6 mbytes/ second (theoretical) ? sustained write: max 6.0 mbytes/s in ata pio mode 4 cycle timing ? sustained read: max 6.5 mbytes/s in ata pio mode 4 cycle timing w/e endurance: 100,000cycles 1 /300,000cycles 2 notes: 1. t a = -40 to 85c 2. t a = 0 to 70c description the wed7pxxxata70xxi25 series ata card is an ata interface ? ash memory card based on ? ash technology. the ata card is constructed with a ? ash disk controller chip and nand-type ? ash memory device. operates from a single 5-volt or 3.3-volt power source. the card is available in ata type-2 form factor with 128mb, 256mb, 128mb to 1gb industrial ata flash 512mb and 1.02gb unformatted capacity. being able to emulate ide hard disk drives, wedcs ata card is a perfect choice for solid-state mass-storage in industrial applications and applications that require performance and extended environmental tolerances. dimensions: type 2 card: 85.6mm(l) x 54.0mm (w) x 5.03mm (h) lead free and rohs compliant storage capacities: 128mb, 256mb, 512mb and 1.02gb (unformatted) operating voltage: 3.3v 5% 5.0v 0.5v power consumption: ? 5v operation active mode: write operation: 28 ma (typ.) read operation: 23 ma (typ.) power down mode: 1.2ma (typ.) 2.0ma (max.) ? 3.3v operation active mode: write operation: 25 ma (typ.) read operation: 21 ma (typ.) power down mode: 1.0ma (typ.) 1.5ma (max.) environment conditions: ? operating temperature: -40c to 85c ? storage temperature: -45c to 90c ? storage humidity: 95% (max) (no condensation) * this product is subject to change without notice. product types card density model no. cylinder head sector memory capacity 1 128mb 7p128ata70xxi25 978 8 32 128,188,416 byte 256mb 7p256ata70xxi25 978 16 32 256,376,832 byte 512mb 7p512ata70xxi25 993 16 63 512,483,328 byte 1.02gb 7p1g0ata70xxi25 1985 16 63 1024,450,560 byte 1: it is the logical address capacity including the area used for file system.
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. pin assignments and pin type pin # memory card mode i/o card mode true ide mode signal name i/o signal name i/o signal name i/o 1gnd gnd gnd 2 d3 i/o d3 i/o d3 i/o 3 d4 i/o d4 i/o d4 i/o 4 d5 i/o d5 i/o d5 i/o 5 d6 i/o d6 i/o d6 i/o 6 d7 i/o d7 i/o d7 i/o 7 ce1# i ce1# i ce1# i 8 a10 i a10 i a10 i 9 oe# i oe# i atasel# i 10 n.c. C n.c. C n.c. C 11a9ia9ia9i 12 a8 i a8 i a8 i 13 n.c. C n.c. C n.c. C 14 n.c. C n.c. C n.c. C 15 we# i we# i we# i 16 rdy/bsy o ireq# o intrq o 17 vcc vcc vcc 18 n.c. C n.c. C n.c. C 19 n.c. C n.c. C n.c. C 20 n.c. C n.c. C n.c. C 21 n.c. C n.c. C n.c. C 22 a7 i a7 i a7 i 23a6ia6ia6i 24 a5 i a5 i a5 i 25 a4 i a4 i a4 i 26a3ia3ia3i 27 a2 i a2 i a2 i 28 a1 i a1 i a1 i 29 a0 i a0 i a0 i 30 d0 i/o d0 i/o d0 i/o 31 d1 i/o d1 i/o d1 i/o 32 d2 i/o d2 i/o d2 i/o 33 wp o iois16# o iois16# o 34 gnd C gnd C gnd C pin # memory card mode i/o card mode true ide mode signal name i/o signal name i/o signal name i/o 35gndCgndCgndC 36 cd1# o cd1# o cd1# o 37 d11 i/o d11 i/o d11 i/o 38 d12 i/o d12 i/o d12 i/o 39 d13 i/o d13 i/o d13 i/o 40 d14 i/o d14 i/o d14 i/o 41 d15 i d15 i d15 i 42 ce2# i ce2# i ce2# i 43 vs1 o vs1 o vs1 o 44 iord# i iord# i iord# i 45 iowr# i iowr# i iowr# i 46 nc C nc C nc C 47 nc C nc C nc C 48 nc C nc C nc C 49 nc C nc C nc C 50 nc C nc C nc C 51 vcc C vcc C vcc C 52 nc C nc C nc C 53 nc C nc C nc C 54 nc C nc C nc C 55 nc C nc C nc C 56 csel# i csel# i csel# i 57 vs2 o vs2 o vs2 o 58 reset i reset i reset# i 59 wait# o wait# o iordy o 60 inpack# o inpack# o inpack# o 61reg#ireg#ireg#i 62 bvd2 i/o spkr# i/o dasp i/o 63 bvd1 i/o stschg# i/o pdiag# i/o 64 d8 i/o d8 i/o d8 i/o 65 d9 i/o d9 i/o d9 i/o 66 d10 o d10 o d10 o 67 cd2# o cd2# o cd2# o 68gndCgndCgndC
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. access specifications 1. attribute access speci? cations when cis-rom region or con? guration register region is accessed, read and write operations are executed under the condition of reg# = l as follows. that region can be accessed by byte/word/odd-byte modes, which are de? ned by pc card standard speci? cations. attribute read access mode mode reg# ce2# ce1# a0 oe# we# d8 to d15 d0 to d7 standby mode x h h x x x high-z high-z byte access (8bit) l h l l l h high-z even byte l h l h l h high-z invalid word access (16bit) l l l x l h invalid even byte odd byte access (8bit) l l h x l h invalid high-z note: x l or h attribute write access mode mode reg# ce2# ce1# a0 oe# we# d8 to d15 d0 to d7 standby mode x h h x x x dont care dont care byte access (8bit) l h l l h l dont care even byte l h l h h l dont care dont care word access (16bit) l l l x h l dont care even byte odd byte access (8bit) l l h x h l dont care dont care note: x l or h write cis-rom region is invalid.
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. 2. task file register access speci? cations there are two types of task file register mapping, one is mapped i/o address area, the other is mapped memory address area. each type of task file register read and write operation is executed under the condition as follows. that area can be accessed by byte/word/odd byte modes, which are de? ned by pc card standard speci? cations. (1) i/o address map C task file register read access mode (1) mode reg# ce2# ce1# a0 iord# iowr# oe# we# d8 to d15 d0 to d7 standby mode x h h xxxxxhigh-zhigh-z byte access (8bit) l h l l l h h h high-z even byte l h l h l h h h high-z odd byte word access (16bit) l l l x l h h h odd byte even byte odd byte access (8bit) l l h x l h h h odd byte high-z note: x l or h task file register write access mode (1) mode reg# ce2# ce1# a0 iord# iowr# oe# we# d8 to d15 d0 to d7 standby mode x h h xxxxxdont caredont care byte access (8bit) l h l l h l h h dont care even byte l h l h h l h h dont care odd byte word access (16bit) l l l x h l h h odd byte even byte odd byte access (8bit) l l h x h l h h odd byte dont care note: x l or h (2) memory address map C task file register read access mode (2) mode reg# ce2# ce1# a0 oe# we# iord# iowr# d8 to d15 d0 to d7 standby mode x h h xxxxxhigh-zhigh-z byte access (8bit) h h l l l h h h high-z even byte h h l h l h h h high-z odd byte word access (16bit) h l l x l h h h odd byte even byte odd byte access (8bit) h l h x l h h h odd byte high-z note: x l or h task file register write access mode (2) mode reg# ce2# ce1# a0 oe# we# iord# iowr# d8 to d15 d0 to d7 standby mode x h h xxxxxdont caredont care byte access (8bit) h h l l h l h h dont care even byte h h l h h l h h dont care odd byte word access (16bit) h l l x h l h h odd byte even byte odd byte access (8bit) h l h x h l h h odd byte dont care note: x l or h
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. 3. true ide mode the card can be con? gured in a true ide. this card is con? gured in this mode only when the oe# input signal is asserted to gnd by the host during power on . in this true ide mode attribute registers are not accessible from the host. only i/o operation to the task ? le and data register is allowed. if this card is con? gured during power on sequence, data register is accessed in word (16-bit). the card permits 8-bit accesses if the user issues a set feature command to put the device in 8-bit mode. true ide mode read i/o function mode ce2# ce1# a0~a2 dmack# dior# diow# d8~d15 d0~d7 invalid mode l l xxxxhigh-zhigh-z standby mode h hxhxxhigh-zhigh-z pio data register access h l 0 h l h odd byte even byte multiword dma data register access h h x l l h odd byte even byte alternate status access l h 6h h l h high-z status out other task ? le access h l 1~7h h l h high-z data note: x l or h true ide mode write i/o function mode ce2# ce1# a0~a2 dmack# dior# diow# d8~d15 d0~d7 invalid mode l l xxxxdont caredont care standby mode h hxhxxdont caredont care pio data register access h l 0 h h l odd byte even byte multiword dma data register access h h x l h l odd byte even byte control register access l h 6h h h l dont care control in other task ? le access h l 1~7h h h l dont care data note: x l or h card system performance item performance set up time (reset to ready) 250 ms (max.) set up time (power down to ready) 5.5 ms (max.) data transfer rate to / from host 16.6 m byte / s burst (max.), theoretically sustained read transfer rate 6.5 m byte / s (max.), actually *1 sustained write transfer rate 6.0 m byte / s (max.), actually *1 command to drq (sector re ad at ready state) 4 ms (max.) command to drq (sector write at ready state) 700 ms (max.) data transfer cycle end to ready (sector write) 2 ms (typ.), 200 ms (max.) auto power down time 1.5s (min.), 1.8s (typ.) notes: 1. the actual transfer rate is measured under ata pio mode 4 with single cycle time as 120ns.
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. electrical specification symbol parameter min max typ unit v in , v out all input / output voltage -0.3 v cc +0.3 v v cc power supply voltage (absolute maximum ratings) -0.6 6.0 v v cc power supply voltage (recommended operation condition) 4.5 5.5 5.0 v 3.135 3.465 3.3 v t opr operating temperature -40 85 c t stg storage temperature -45 90 c input leakage current type symbol parameter condition min max typ unit notes ixz il input leakage current v ih = vcc / v il = gnd -1 1 a *1 ixu rpu1 pull up resistor vcc = 5.0v 50 500 k? *1 ixd rpd1 pull down resister vcc = 5.0v 50 500 k? *1 notes: 1. x refers to the characteristics described in section dc characteristics ( input characteristics). for example, i1u indicat es a pull up resister with a type 1 input characteristics. output drive type type output type valid conditions notes otx totempole i oh & i ol *1 ozx tri-state n-p channel i oh & i ol *1 opx p-channel only i oh only *1 onx n-channel only i ol only *1 notes: 1. x refers to the characteristics described in section dc characteristics ( output drive characteristics). fo r example, ot1 refers to totempole output with a type 1 output drive characteristics.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. dc characteristics v cc = 3.3 v 5%, 5 v 0.5v, -40c t a 85c symbol parameter min max typ. unit test conditions i li input leakage current 1 a i lo output leakage current 1 a v out = high impedance i pu pull-up current (resistivity) 43 (75) a (k?) v force = 3.3v i pd pull-down current (resistivity) -43 (75) a (k?) v force = 0v i ccs power down mode current 1.5 2.0 1.0 1.2 ma v cc = 3.3v v cc = 5v i cco operating current @ 3.3v write operation read operation 25 21 ma v cc = 3.3v operation operating current @ 5v write operation read operation 28 23 ma v cc = 5v operation input characteristics type symbol parameter min max typ unit condition 1 v ih input high voltage cmos 2.0 2.0 v v cc = 3.3 v v cc = 5 v v il input low voltage cmos 1.0 1.0 v cc = 3.3 v v cc = 5 v 2 v ih input high voltage 2.0 2.0 v cc = 3.3 v v cc = 5 v v il input low voltage cmos 1.0 0.8 v cc = 3.3 v v cc = 5 v 3 v t+ input low to high threshold schmitt trigger 2.5 2.5 2.1 2.1 v cc = 3.3 v v cc = 5 v v t- input high to low threshold schmitt trigger 0.9 0.9 1.2 1.2 v cc = 3.3 v v cc = 5 v v t hysteresis voltage 0.5 0.8 v cc = 3.3 v v cc = 5 v 4 v t+ input low to high threshold schmitt trigger 2.3 2.0 2.1 1.8 v cc = 3.3 v v cc = 5 v v t- input high to low threshold schmit trigger 1.0 0.8 1.2 1.1 v cc = 3.3 v v cc = 5 v v t hysteresis voltage 0.5 0.8 v cc = 3.3 v v cc = 5 v output drive characteristics type symbol parameter min max typ unit condition 1 v oh output high voltage v cc - 0.8 v i oh = -4ma i ol = 4ma v ol output low voltage gnd + 0.4
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics v cc = 3.3 v 5%, 5 v 0.5v, -40c t a 85c attribute memory read ac characteristics symbol parameter min max unit t c read cycle time 250 ns t a address access time 250 t a ce# access time 250 t a oe# access time 125 t dis output disable time (ce#) 100 t dis output disable time (oe#) 100 t en output enable time (ce#) 5 t en output enable time (oe#) 5 t v data valid time (a) 0 t su address setup time 30 attribute memory write ac characteristics symbol parameter min max unit t c write cycle time 250 ns t w write pulse time 150 t su address setup time 30 t su data setup time (-we) 80 t h data hold time 30 t rec write recover time 30 i/o access read ac characteristics symbol parameter min max unit t d data delay after iord# 100 ns t h data hold following iord# 0 t w iord# pulse width 165 t su a address setup before iord# 70 t h a address hold following iord# 20 t su ce ce# setup before iord# 5 t h ce ce# hold following iord# 20 t su reg reg# setup before iord# 5 t h reg reg# hold following -iord 0 t df inpack inpack# delay failing from iord# 0 45 t dr inpack inpack# delay rising from iord# 45 t df iois1 6 iois#16 delay failing from address 35 t dr iois16 iois#16 delay rising from address 35
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. i/o access write ac characteristics symbol parameter min max unit t su data setup before iowr# 60 ns t h data hold following iowr# 30 t w iowr# pulse width 165 t su a address setup before iowr# 70 t h a address hold following iowr# 20 t su ce ce# setup before iowr# 5 t h ce ce# hold following iowr# 20 t su reg reg# setup before iowr# 5 t h reg reg# hold following iowr# 0 t df iois16 iois16# delay failing from address 35 t dr iois16 iois16# delay rising from address 35 common memory access read ac characteristics symbol parameter min max unit t a oe# access time 125 ns t dis output disable time (oe#) 100 t su address setup time 30 t h address hold time 20 t su ce# setup before oe# 0 t h oe# hold following oe# 20 common memory access write ac characteristics symbol parameter min max unit t su data setup before we# 80 ns t h data hold following we# 30 t w write pulse width 150 t h address hold time 20 t su address setup time 30 t su ce# setup time 0 t rec write recover time 30 t h ce# hold following we# 20
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. true ide mode io read/write ac characteristics symbol parameter min max unit t0 cycle time 120 ns t1 address valid to -diow/-dior setup 25 t2 diow#/-dior 70 t2 diow#/-dior register (8bit) 70 t2i diow#/-dior recoverry time 25 t3 diow# data setup 20 t4 diow# data hold 10 t5 dior# data setup 20 t6 dior# data hold 5 t6z dior# data tristate 30 t7 address valid to -iois16 assertion 35 t8 address valid to -iois16 released 35 t9 diow#/-dior to address valid hold 10 true ide mode multiword dma read/write ac characteristics symbol parameter min max unit t0 cycle time 120 ns td dior#/diow# assert width 70 te dior# data access 50 tf dior# data hold 5 tg diow#/dior# data setup 20 th diow# data hold 10 ti dmack# to dior#/diow# setup 0 tj dior#/diow# to dmack hold 5 tkr dior# negated width 25 tkw diow# negated width 25 tlr dior# to dmarq delay 35 tlw diow# to dmarq delay 35 tm cs0#/cs1# valid to -dior#/-diow# 25 tn cs0#/cs1# hold 10 tz dmack# to read data released 25
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. reset characteristics (only memory card mode or i/o card mode) symbol parameter min max unit t su reset setup time 100 m s t rec ce# recover time 1 s t pr v cc rising up time 0.1 100 m s t pf v cc falling down time 3 300 m s t w reset pulse width 10 s t h 1m s t s 0m s power on reset characteristics power on reset sequence must need by porst# at the rising edge of v cc . symbol parameter min max unit t su ce# setup time 100 m s t pr v cc rising up time 0.1 100 m s
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. package dimensions interconnect area substrate area 1.6mm 0.05 (0.063) 1.0mm 0.05 (0.039) 1.0mm 0.05 (0.039) 3.3mm 0.10 (0.129) 85.6mm 0.20 (3.370) 54.0mm 0.10 (2.126) 3.0mm min (0.118) 5.0mm t1 (0.197) 10.0mm min (0.400) type ii
13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. attention for card use ? in the reset or power off mode, the information in all registers are cleared. ? note that the card insertion/removal should not be executed while host is active if the card is used in true ide mode. ? after the hard reset, soft reset or power-on reset or ata reset command is applied the card cannot be accessed while ready pin is low. flash card cant be operated in this mode. ? before insertion v cc cannot be supplied to the card. after con? rmation that cd1#, cd2# pins are set, v cc may be supplied to the card. ? oe# must be kept at the v cc level during power on reset in memory card mode and i/o card mode. oe must be kept constantly at the gnd level in true ide mode. ? do not turn off the power or remove wed7pxxxata70xxi25 series from the slot before read/write operation is complete. avoid using wed7pxxxata70xxi25 series when the battery is low. power shortage, power failure and/or removal of wed7pxxxata70xxi25 series from the slot before read/write operation is complete may cause malfunction of wed7pxxxata70xxi25 series, data loss and/or damage to data. ? routine performance of backing-up data (or taking back-up of data) is strongly recommended.
14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. part numbering guide wed 7p xxx ata 70 xx i 25 wedc flash memory size ata flash industrial flash housing: 03 = wedc logo 04 = blank housing enhanced industrial temp speed
15 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxata70xxi25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. document title 128mb to 1gb industrial ata flash revision history rev # history release date status rev 0 initial release march 2005 final rev 1 1.1 added "ed" to part marking july 2005 final

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